Comparative Analysis of 11T and 16T and 28T Full Adder Based 4*4 Wallace Tree Multiplier Using Cadence 180nm Technology

1 Associate Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India. 2 Assistant Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India ---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Multiplier is an important key component used for arithmetic operations in digital signal processor. Power utilization in multiplier is more when compared with adders and subtractors. So decreasing the power utilization of multiplier makes a digital signal processor more efficient. A Wallace tree multiplier is an efficient high speed multiplier that multiples two integers. Here 4*4 wallace tree multiplier is proposed with eight full adders and four half adders. Each full adder used in this design has only eleven(11T) transistors and half adder used in this design has only 10 Transistors which is less in number when compared with the conventional full adders. Due to this the power utilization of full adder block is reduced, such that power utilization of 4*4 wallace tree multiplier will be decreased. The proposed design this simulated using 180nm technology in cadence virtuoso tool and has achieved up to 50% power saving in comparison to the Wallace Tree Multiplier that has been designed using Conventional Full adder.